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Table of Contents

• 1. Hardware Drivers
• 1.1. Parport
• 1.1.1. Installing
• 1.1.2. Pins
• 1.1.3. Parameters
• 1.1.4. Functions
• 1.1.5. Common problems
• 1.2. probe_parport
• 1.2.1. Installing
• 1.3. AX5214H
• 1.3.1. Installing
• 1.3.2. Pins
• 1.3.3. Parameters
• 1.3.4. Functions
• 1.4. Servo-To-Go
• 1.4.1. Installing:
• 1.4.2. Pins
• 1.4.3. Parameters
• 1.4.4. Functions
• 1.5. Mesa Electronics m5i20 “Anything I/O Card”
• 1.5.1. Pins
• 1.5.2. Parameters
• 1.5.3. Functions
• 1.5.4. Connector pinout
• 1.6. Vital Systems Motenc-100 and Motenc-LITE
• 1.6.1. Pins
• 1.6.2. Parameters
• 1.6.3. Functions
• 1.7. Pico Systems PPMC (Parallel Port Motion Control)
• 1.7.1. Pins
• 1.7.2. Parameters
• 1.7.3. Functions
• 1.8. Pluto-P: generalities
• 1.8.1. Requirements
• 1.8.2. Connectors
• 1.8.3. Physical Pins
• 1.8.4. LED
• 1.8.5. Power
• 1.8.6. PC interface
• 1.8.7. Rebuilding the FPGA firmware
• 1.8.8. For more information
• 1.9. pluto-servo: Hardware PWM and quadrature counting
• 1.9.1. Pinout
• 1.9.2. Input latching and output updating
• 1.9.3. HAL Functions, Pins and Parameters
• 1.9.4. Compatible driver hardware
• 1.10. Pluto-step: 300kHz Hardware Step Generator
• 1.10.1. Pinout
• 1.10.2. Input latching and output updating
• 1.10.3. Step Waveform Timings
• 1.10.4. HAL Functions, Pins and Parameters

List of figures

• Parport Block Diagram
• Pluto-Servo Pinout
• Pluto-Step Pinout
• Pluto-Step Timings

List of tables

• Pluto-Servo Alternate Pin Functions

1 Hardware Drivers

1.1 Parport

Parport is a driver for the traditional PC parallel port. The port has a total of 17 physical pins. The original parallel port divided those pins into three groups: data, control, and status. The data group consists of 8 output pins, the control group consists of 4 pins, and the status group consists of 5 input pins.

In the early 1990's, the bidirectional parallel port was introduced, which allows the data group to be used for output or input. The HAL driver supports the bidirectional port, and allows the user to set the data group as either input or output. If configured as output, a port provides a total of 12 outputs and 5 inputs. If configured as input, it provides 4 outputs and 13 inputs.

In some parallel ports, the control group pins are open collectors, which may also be driven low by an external gate. On a board with open collector control pins, the “x” mode allows a more flexible mode with 8 dedicated outputs, 5 dedicated inputs, and 4 open collector pins. In other parallel ports, the control group has push-pull drivers and cannot be used as an input.¹

No other combinations are supported, and a port cannot be changed from input to output once the driver is installed. Figure [.] shows two block diagrams, one showing the driver when the data group is configured for output, and one showing it configured for input.

The parport driver can control up to 8 ports (defined by MAX_PORTS in hal_parport.c). The ports are numbered starting at zero.

1.1.1 Installing

loadrt hal_parport cfg="<config-string>"

The config string consists of a hex port address, followed by an optional direction, repeated for each port. The direction is “in”, “out”, or “x” and determines the direction of the physical pins 2 through 9, and whether to create input HAL pins for the physical control pins. If the direction is not specified, the data group defaults to output. For example:

loadrt hal_parport cfg="0x278 0x378 in 0x20A0 out"

This example installs drivers for one port at 0x0278, with pins 2-9 as outputs (by default, since neither “in” nor “out” was specified), one at 0x0378, with pins 2-9 as inputs, and one at 0x20A0, with pins 2-9 explicitly specified as outputs. Note that you must know the base address of the parallel port to properly configure the driver. For ISA bus ports, this is usually not a problem, since the port is almost always at a “well known” address, like 0278 or 0378 which is typically configured in the system BIOS. The address for a PCI card is usally shown in “lspci -v” in an “I/O ports” line, or in the kernel message log after executing “sudo modprobe -a parport_pc”. There is no default address; if <config-string> does not contain at least one address, it is an error.

Figure: Parport Block Diagram

1.1.2 Pins

• (bit) parport.<portnum>.pin-<pinnum>-out -- Drives a physical output pin.
• (bit) parport.<portnum>.pin-<pinnum>-in -- Tracks a physical input pin.
• (bit) parport.<portnum>.pin-<pinnum>-in-not -- Tracks a physical input pin, but inverted.

For each pin, <portnum> is the port number, and <pinnum> is the physical pin number in the 25 pin D-shell connector.

For each physical output pin, the driver creates a single HAL pin, for example parport.0.pin-14-out. Pins 2 through 9 are part of the data group and are output pins if the port is defined as an output port. (Output is the default.) Pins 1, 14, 16, and 17 are outputs in all modes. These HAL pins control the state of the corresponding physical pins.

For each physical input pin, the driver creates two HAL pins, for example parport.0.pin-12-in and parport.0.pin-12-in-not. Pins 10, 11, 12, 13, and 15 are always input pins. Pins 2 through 9 are input pins only if the port is defined as an input port. The -in HAL pin is TRUE if the physical pin is high, and FALSE if the physical pin is low. The -in-not HAL pin is inverted -- it is FALSE if the physical pin is high. By connecting a signal to one or the other, the user can determine the state of the input. In “x” mode, pins 1, 14, 16, and 17 are also input pins.

1.1.3 Parameters

• (bit) parport.<portnum>.pin-<pinnum>-out-invert -- Inverts an output pin.
• (bit) parport.<portnum>.pin-<pinnum>-out-reset (only for pins 2..9) -- TRUE if this pin should be reset when the -reset function is executed.
• (U32) parport.<portnum>.reset-time -- The time (in nanoseconds) between a pin is set by write and reset by reset HAL functions.

The -invert parameter determines whether an output pin is active high or active low. If -invert is FALSE, setting the HAL -out pin TRUE drives the physical pin high, and FALSE drives it low. If -invert is TRUE, then setting the HAL -out pin TRUE will drive the physical pin low.

If -reset is TRUE, then the reset function will set the pin to the value of -out-invert. This can be used in conjunction with stepgen's doublefreq to produce one step per period.

1.1.4 Functions

• (funct) parport.<portnum>.read-- Reads physical input pins of port <portnum> and updates HAL -in and -in-not pins.
• (funct) parport.read-all -- Reads physical input pins of all ports and updates HAL -in and -in-not pins.
• (funct) parport.<portnum>.write -- Reads HAL -out pins of port <portnum> and updates that port's physical output pins.
• (funct) parport.write-all -- Reads HAL -out pins of all ports and updates all physical output pins.
• (funct) parport.<portnum>.reset -- Waits until reset-time has elapsed since the associated write, then resets pins to values indicated by -out-invert and -out-invert settings. reset must be later in the same thread as write

The individual functions are provided for situations where one port needs to be updated in a very fast thread, but other ports can be updated in a slower thread to save CPU time. It is probably not a good idea to use both an -all function and an individual function at the same time.

1.1.5 Common problems

If loading the module reports

insmod: error inserting '/home/jepler/emc2/rtlib/hal_parport.ko':
-1 Device or resource busy 

then ensure that the standard kernel module parport_pc is not loaded² and that no other device in the system has claimed the I/O ports.

If the module loads but does not appear to function, then the port address is incorrect or the probe_parport module is required.

1.2 probe_parport

In modern PCs, the parallel port may require plug and play (PNP) configuration before it can be used. The probe_parport module performs configuration of any PNP ports present, and should be loaded before hal_parport. On machines without PNP ports, it may be loaded but has no effect.

1.2.1 Installing

loadrt probe_parport
loadrt hal_parport ...

If the Linux kernel prints a message similar to

parport: PnPBIOS parport detected.

when the parport_pc module is loaded (sudo modprobe -a parport_pc; sudo rmmod parport_pc) then use of this module is probably required.

1.3 AX5214H

The Axiom Measurement & Control AX5214H is a 48 channel digital I/O board. It plugs into an ISA bus, and resembles a pair of 8255 chips.³

1.3.1 Installing

loadrt hal_ax5214h cfg="<config-string>"

The config string consists of a hex port address, followed by an 8 character string of “I” and “O” which sets groups of pins as inputs and outputs. The first two character set the direction of the first two 8 bit blocks of pins (0-7 and 8-15). The next two set blocks of 4 pins (16-19 and 20-23). The pattern then repeats, two more blocks of 8 bits (24-31 and 32-39) and two blocks of 4 bits (40-43 and 44-47). If more than one board is installed, the data for the second board follows the first. As an example, the string "0x220 IIIOIIOO 0x300 OIOOIOIO" installs drivers for two boards. The first board is at address 0x220, and has 36 inputs (0-19 and 24-39) and 12 outputs (20-23 and 40-47). The second board is at address 0x300, and has 20 inputs (8-15, 24-31, and 40-43) and 28 outputs (0-7. 16-23, 32-39, and 44-47). Up to 8 boards may be used in one system.

1.3.2 Pins

• (bit) ax5214.<boardnum>.out-<pinnum> -- Drives a physical output pin.
• (bit) ax5214.<boardnum>.in-<pinnum> -- Tracks a physical input pin.
• (bit) ax5214.<boardnum>.in-<pinnum>-not -- Tracks a physical input pin, inverted.

For each pin, <boardnum> is the board number (starts at zero), and <pinnum> is the I/O channel number (0 to 47).

Note that the driver assumes active LOW signals. This is so that modules such as OPTO-22 will work correctly (TRUE means output ON, or input energized). If the signals are being used directly without buffering or isolation the inversion needs to be accounted for. The in- HAL pin is TRUE if the physical pin is low (OPTO-22 module energized), and FALSE if the physical pin is high (OPTO-22 module off). The in-<pinnum>-not HAL pin is inverted -- it is FALSE if the physical pin is low (OPTO-22 module energized). By connecting a signal to one or the other, the user can determine the state of the input.

1.3.3 Parameters

• (bit) ax5214.<boardnum>.out-<pinnum>-invert -- Inverts an output pin.

The -invert parameter determines whether an output pin is active high or active low. If -invert is FALSE, setting the HAL out- pin TRUE drives the physical pin low, turning ON an attached OPTO-22 module, and FALSE drives it high, turning OFF the OPTO-22 module. If -invert is TRUE, then setting the HAL out- pin TRUE will drive the physical pin high and turn the module OFF.

1.3.4 Functions

• (funct) ax5214.<boardnum>.read -- Reads all digital inputs on one board.
• (funct) ax5214.<boardnum>.write -- Writes all digital outputs on one board.

1.4 Servo-To-Go

The Servo-To-Go is one of the first PC motion control cards⁴ supported by EMC. It is an ISA card and it exists in different flavours (all supported by this driver). The board includes up to 8 channels of quadrature encoder input, 8 channels of analog input and output, 32 bits digital I/O, an interval timer with interrupt and a watchdog.

1.4.1 Installing:

loadrt hal_stg [base=<address>] [num_chan=<nr>] [dio="<dio-string>"] [model=<model>]

The base address field is optional; if it's not provided the driver attempts to autodetect the board. The num_chan field is used to specify the number of channels available on the card, if not used the 8 axis version is assumed. The digital inputs/outputs configuration is determined by a config string passed to insmod when loading the module. The format consists of a four character string that sets the direction of each group of pins. Each character of the direction string is either "I" or "O". The first character sets the direction of port A (Port A - DIO.0-7), the next sets port B (Port B - DIO.8-15), the next sets port C (Port C - DIO.16-23), and the fourth sets port D (Port D - DIO.24-31). The model field can be used in case the driver doesn't autodetect the right card version⁵. For example:

loadrt hal_stg base=0x300 num_chan=4 dio="IOIO"

This example installs the stg driver for a card found at the base address of 0x300, 4 channels of encoder feedback, DAC's and ADC's, along with 32 bits of I/O configured like this: the first 8 (Port A) configured as Input, the next 8 (Port B) configured as Output, the next 8 (Port C) configured as Input, and the last 8 (Port D) configured as Output

loadrt hal_stg

This example installs the driver and attempts to autodetect the board address and board model, it installs 8 axes by default along with a standard I/O setup: Port A & B configured as Input, Port C & D configured as Output.

1.4.2 Pins

• (s32) stg.<channel>.counts -- Tracks the counted encoder ticks.
• (float) stg.<channel>.position -- Outputs a converted position.
• (float) stg.<channel>.dac-value -- Drives the voltage for the corresponding DAC.
• (float) stg.<channel>.adc-value -- Tracks the measured voltage from the corresponding ADC.
• (bit) stg.in-<pinnum> -- Tracks a physical input pin.
• (bit) stg.in-<pinnum>-not -- Tracks a physical input pin, but inverted.
• (bit) stg.out-<pinnum> -- Drives a physical output pin

For each pin, <channel> is the axis number, and <pinnum> is the logic pin number of the STG⁶.

The in- HAL pin is TRUE if the physical pin is high, and FALSE if the physical pin is low. The in-<pinnum>-not HAL pin is inverted -- it is FALSE if the physical pin is high. By connecting a signal to one or the other, the user can determine the state of the input.

1.4.3 Parameters

• (float) stg.<channel>.position-scale -- The number of counts / user unit (to convert from counts to units).
• (float) stg.<channel>.dac-offset -- Sets the offset for the corresponding DAC.
• (float) stg.<channel>.dac-gain -- Sets the gain of the corresponding DAC.
• (float) stg.<channel>.adc-offset -- Sets the offset of the corresponding ADC.
• (float) stg.<channel>.adc-gain -- Sets the gain of the corresponding ADC.
• (bit) stg.out-<pinnum>-invert -- Inverts an output pin.

The -invert parameter determines whether an output pin is active high or active low. If -invert is FALSE, setting the HAL out- pin TRUE drives the physical pin high, and FALSE drives it low. If -invert is TRUE, then setting the HAL out- pin TRUE will drive the physical pin low.

1.4.4 Functions

• (funct) stg.capture-position -- Reads the encoder counters from the axis <channel>.
• (funct) stg.write-dacs -- Writes the voltages to the DACs.
• (funct) stg.read-adcs -- Reads the voltages from the ADCs.
• (funct) stg.di-read -- Reads physical in- pins of all ports and updates all HAL in- and in-<pinnum>-not pins.
• (funct) stg.do-write -- Reads all HAL out- pins and updates all physical output pins.

1.5 Mesa Electronics m5i20 “Anything I/O Card”

The Mesa Electronics m5i20 card consists of an FPGA that can be loaded with a wide variety of configurations, and has 72 pins that leave the PC. The assignment of the pins depends on the FPGA configuration. Currently there is a HAL driver for the “4 axis host based motion control” configuration, and this FPGA configurations is also provided with EMC2. It provides 8 encoder counters, 4 PWM outputs (normally used as DACs) and up to 48 digital I/O channels, 32 inputs and 16 outputs.⁷

Installing:

loadrt hal_m5i20 [loadFpga=1|0] [dacRate=<rate>]

If loadFpga is 1 (the default) the driver will load the FPGA configuration on startup. If it is 0, the driver assumes the configuration is already loaded. dacRate sets the carrier frequency for the PWM outputs, in Hz. The default is 32000, for 32KHz PWM. Valid values are from 1 to 32226. The driver prints some useful debugging message to the kernel log, which can be viewed with dmesg.

Up to 4 boards may be used in one system.

1.5.1 Pins

In the following pins, parameters, and functions, <board> is the board ID. According to the naming conventions the first board should always have an ID of zero, however this driver uses the PCI board ID, so it may be non-zero even if there is only one board.

• (s32) m5i20.<board>.enc-<channel>-count -- Encoder position, in counts.
• (float) m5i20.<board>.enc-<channel>-position -- Encoder position, in user units.
• (bit) m5i20.<board>.enc-<channel>-index -- Current status of index pulse input?
• (bit) m5i20.<board>.enc-<channel>-index-enable -- when true, and an index pulse appears on the encoder input, reset counter to zero and clear index-enable.
• (bit) m5i20.<board>.enc-<channel>-reset -- When true, counter is forced to zero.
• (bit) m5i20.<board>.dac-<channel>-enable -- Enables DAC if true. DAC outputs zero volts if false?
• (float) m5i20.<board>.dac-<channel>-value -- Analog output value for PWM “DAC” (in user units, see -scale and -offset)
• (bit) m5i20.<board>.in-<channel> -- State of digital input pin, see canonical digital input.
• (bit) m5i20.<board>.in-<channel>-not -- Inverted state of digital input pin, see canonical digital input.
• (bit) m5i20.<board>.out-<channel> -- Value to be written to digital output, see canonical digital output.
• (bit) m5i20.<board>.estop-in -- Dedicated estop input, more details needed.
• (bit) m5i20.<board>.estop-in-not -- Inverted state of dedicated estop input.
• (bit) m5i20.<board>.watchdog-reset -- Bidirectional, - Set TRUE to reset watchdog once, is automatically cleared. If bit value 16 is set in watchdog-control then this value is not used, and the hardware watchdog is cleared every time the dac-write function is executed.

1.5.2 Parameters

• (float) m5i20.<board>.enc-<channel>-scale -- The number of counts / user unit (to convert from counts to units).
• (float) m5i20.<board>.dac-<channel>-offset -- Sets the DAC offset.
• (float) m5i20.<board>.dac-<channel>-gain -- Sets the DAC gain (scaling).
• (bit) m5i20.<board>.dac-<channel>-interlaced -- Sets the DAC to interlaced mode. Use this mode if you are filtering the PWM to generate an anaolg voltage.⁸
• (bit) m5i20.<board>.out-<channel>-invert -- Inverts a digital output, see canonical digital output.
• (u32) m5i20.<board>.watchdog-control -- Configures the watchdog. The value may be a bitwise OR of the following values:
  

  Bit #	Value	Meaning
  0	1	Watchdog is enabled
  1	2	Watchdog is automatically reset by DAC writes (the HAL dac-write function)

  Typically, the useful values are 0 (watchdog disabled) or 3 (watchdog enabled, cleared by dac-write).
• (u32) m5i20.<board>.led-view -- Maps some of the I/O to onboard LEDs. See table below.

1.5.3 Functions

• (funct) m5i20.<board>.encoder-read -- Reads all encoder counters.
• (funct) m5i20.<board>.digital-in-read -- Reads digital inputs.
• (funct) m5i20.<board>.dac-write -- Writes the voltages (PWM duty cycles) to the “DACs”.
• (funct) m5i20.<board>.digital-out-write -- Writes digital outputs.
• (funct) m5i20.<board>.misc-update -- Writes watchdog timer configuration to hardware. Resets watchdog timer. Updates E-stop pin (more info needed). Updates onboard LEDs.

1.5.4 Connector pinout

The Hostmot-4 FPGA configuration has the following pinout. There are three 50-pin ribbon cable connectors on the card: P2, P3, and P4. There are also 8 status LEDs.

1.5.4.1 Connector P2

1.5.4.2 Connector P3

Encoder counters 4 - 7 work simultaneously with in-00 to in-11.

If you are using in-00 to in-11 as general purpose IO then reading enc-<4-7> will produce some random junk number.

1.5.4.3 Connector P4

The index mask masks the index input of the encoder so that the encoder index can be combined with a mechanical switch or opto detector to clear or latch the encoder counter only when the mask input bit is in proper state (selected by mask polarity bit) and encoder index occurs. This is useful for homing. The behaviour of these pins is controlled by the Counter Control Register (CCR), however there is currently no function in the driver to change the CCR. See REGMAP4⁹ for a description of the CCR.

1.5.4.4 LEDs

The status LEDs will monitor one motion channel set by the m5i20.<board>.led-view parameter. A call to m5i20.<board>.misc-update is required to update the viewed channel.

1.6 Vital Systems Motenc-100 and Motenc-LITE

The Vital Systems Motenc-100 and Motenc-LITE are 8- and 4-channel servo control boards. The Motenc-100 provides 8 quadrature encoder counters, 8 analog inputs, 8 analog outputs, 64 (68?) digital inputs, and 32 digital outputs. The Motenc-LITE has only 4 encoder counters, 32 digital inputs and 16 digital outputs, but it still has 8 analog inputs and 8 analog outputs. The driver automatically identifies the installed board and exports the appropriate HAL objects.¹⁰

Installing:

loadrt hal_motenc

During loading (or attempted loading) the driver prints some usefull debugging message to the kernel log, which can be viewed with dmesg.

Up to 4 boards may be used in one system.

1.6.1 Pins

In the following pins, parameters, and functions, <board> is the board ID. According to the naming conventions the first board should always have an ID of zero. However this driver sets the ID based on a pair of jumpers on the baord, so it may be non-zero even if there is only one board.

• (s32) motenc.<board>.enc-<channel>-count -- Encoder position, in counts.
• (float) motenc.<board>.enc-<channel>-position -- Encoder position, in user units.
• (bit) motenc.<board>.enc-<channel>-index -- Current status of index pulse input.
• (bit) motenc.<board>.enc-<channel>-idx-latch -- Driver sets this pin true when it latches an index pulse (enabled by latch-index). Cleared by clearing latch-index.
• (bit) motenc.<board>.enc-<channel>-latch-index -- If this pin is true, the driver will reset the counter on the next index pulse.
• (bit) motenc.<board>.enc-<channel>-reset-count -- If this pin is true, the counter will immediately be reset to zero, and the pin will be cleared.
• (float) motenc.<board>.dac-<channel>-value -- Analog output value for DAC (in user units, see -gain and -offset)
• (float) motenc.<board>.adc-<channel>-value -- Analog input value read by ADC (in user units, see -gain and -offset)
• (bit) motenc.<board>.in-<channel> -- State of digital input pin, see canonical digital input.
• (bit) motenc.<board>.in-<channel>-not -- Inverted state of digital input pin, see canonical digital input.
• (bit) motenc.<board>.out-<channel> -- Value to be written to digital output, seen canonical digital output.
• (bit) motenc.<board>.estop-in -- Dedicated estop input, more details needed.
• (bit) motenc.<board>.estop-in-not -- Inverted state of dedicated estop input.
• (bit) motenc.<board>.watchdog-reset -- Bidirectional, - Set TRUE to reset watchdog once, is automatically cleared.

1.6.2 Parameters

• (float) motenc.<board>.enc-<channel>-scale -- The number of counts / user unit (to convert from counts to units).
• (float) motenc.<board>.dac-<channel>-offset -- Sets the DAC offset.
• (float) motenc.<board>.dac-<channel>-gain -- Sets the DAC gain (scaling).
• (float) motenc.<board>.adc-<channel>-offset -- Sets the ADC offset.
• (float) motenc.<board>.adc-<channel>-gain -- Sets the ADC gain (scaling).
• (bit) motenc.<board>.out-<channel>-invert -- Inverts a digital output, see canonical digital output.
• (u32) motenc.<board>.watchdog-control -- Configures the watchdog. The value may be a bitwise OR of the following values:
  

  Bit #	Value	Meaning
  0	1	Timeout is 16ms if set, 8ms if unset
  2	4	Watchdog is enabled
  4	16	Watchdog is automatically reset by DAC writes (the HAL dac-write function)

  Typically, the useful values are 0 (watchdog disabled) or 20 (8ms watchdog enabled, cleared by dac-write).
• (u32) motenc.<board>.led-view -- Maps some of the I/O to onboard LEDs?

1.6.3 Functions

• (funct) motenc.<board>.encoder-read -- Reads all encoder counters.
• (funct) motenc.<board>.adc-read -- Reads the analog-to-digital converters.
• (funct) motenc.<board>.digital-in-read -- Reads digital inputs.
• (funct) motenc.<board>.dac-write -- Writes the voltages to the DACs.
• (funct) motenc.<board>.digital-out-write -- Writes digital outputs.
• (funct) motenc.<board>.misc-update -- Updates misc stuff.

1.7 Pico Systems PPMC (Parallel Port Motion Control)

Pico Systems has a family of boards for doing servo, stepper, and pwm control. The boards connect to the PC through a parallel port working in EPP mode. Although most users connect one board to a parallel port, in theory any mix of up to 8 or 16 boards can be used on a single parport. One driver serves all types of boards. The final mix of I/O depends on the connected board(s). The driver doesn't distinguish between boards, it simply numbers I/O channels (encoders, etc) starting from 0 on the first card.

Installing:

loadrt hal_ppmc port_addr=<addr1>[,<addr2>[,<addr3>...]]

The port_addr parameter tells the driver what parallel port(s) to check. By default, <addr1> is 0x0378, and <addr2> and following are not used. The driver searches the entire address space of the enhanced parallel port(s) at port_addr, looking for any board(s) in the PPMC family. It then exports HAL pins for whatever it finds. During loading (or attempted loading) the driver prints some usefull debugging message to the kernel log, which can be viewed with dmesg.

Up to 3 parport busses may be used, and each bus may have up to 8 devices on it.

1.7.1 Pins

In the following pins, parameters, and functions, <board> is the board ID. According to the naming conventions the first board should always have an ID of zero. However this driver sets the ID based on a pair of jumpers on the baord, so it may be non-zero even if there is only one board.

• (s32) ppmc.<port>.encoder.<channel>.count -- Encoder position, in counts.
• (s32) ppmc.<port>.encoder.<channel>.delta -- Change in counts since last read.
• (float) ppmc.<port>.encoder.<channel>.position -- Encoder position, in user units.
• (bit) ppmc.<port>.encoder.<channel>.index -- Something to do with index pulse.¹¹
• (bit) ppmc.<port>.pwm.<channel>.enable -- Enables a PWM generator.
• (float) ppmc.<port>.pwm.<channel>.value -- Value which determines the duty cycle of the PWM waveforms. The value is divided by pwm.<channel>.scale, and if the result is 0.6 the duty cycle will be 60%, and so on. Negative values result in the duty cycle being based on the absolute value, and the direction pin is set to indicate negative.
• (bit) ppmc.<port>.stepgen.<channel>.enable -- Enables a step pulse generator.
• (float) ppmc.<port>.stepgen.<channel>.velocity -- Value which determines the step frequency. The value is multiplied by stepgen.<channel>.scale, and the result is the frequency in steps per second. Negative values result in the frequency being based on the absolute value, and the direction pin is set to indicate negative.
• (bit) ppmc.<port>.in-<channel> -- State of digital input pin, see canonical digital input.
• (bit) ppmc.<port>.in.<channel>-not -- Inverted state of digital input pin, see canonical digital input.
• (bit) ppmc.<port>.out-<channel> -- Value to be written to digital output, seen canonical digital output.

1.7.2 Parameters

• (float) ppmc.<port>.enc.<channel>.scale -- The number of counts / user unit (to convert from counts to units).
• (float) ppmc.<port>.pwm.<channel-range>.freq -- The PWM carrier frequency, in Hz. Applies to a group of four consecutive PWM generators, as indicated by <channel-range>. Minimum is 153Hz, maximum is 500KHz.
• (float) ppmc.<port>.pwm.<channel>.scale -- Scaling for PWM generator. If scale is X, then the duty cycle will be 100% when the value pin is X (or -X).
• (float) ppmc.<port>.pwm.<channel>.max-dc -- Maximum duty cycle, from 0.0 to 1.0.
• (float) ppmc.<port>.pwm.<channel>.min-dc -- Minimum duty cycle, from 0.0 to 1.0.
• (float) ppmc.<port>.pwm.<channel>.duty-cycle -- Actual duty cycle (used mostly for troubleshooting.)
• (bit) ppmc.<port>.pwm.<channel>.bootstrap -- If true, the PWM generator will generate a short sequence of pulses of both polarities when it is enabled, to charge the bootstrap capacators used on some MOSFET gate drivers.
• (u32) ppmc.<port>.stepgen.<channel-range>.setup-time -- Sets minimum time between direction change and step pulse, in units of 100nS. Applies to a group fof four consecutive PWM generators, as indicated by <channel-range>.
• (u32) ppmc.<port>.stepgen.<channel-range>.pulse-width -- Sets width of step pulses, in units of 100nS. Applies to a group fof four consecutive PWM generators, as indicated by <channel-range>.
• (u32) ppmc.<port>.stepgen.<channel-range>.pulse-space-min -- Sets minimum time between pulses, in units of 100nS. The maximum step rate is 1/( 100nS * ( pulse-width + pulse-space-min )). Applies to a group fof four consecutive PWM generators, as indicated by <channel-range>.
• (float) ppmc.<port>.stepgen.<channel>.scale -- Scaling for step pulse generator. The step frequency in Hz is the absolute value of velocity * scale.
• (float) ppmc.<port>.stepgen.<channel>.max-vel -- The maximum value for velocity. Commands greater than max-vel will be clamped. Also applies to negative values. (The absolute value is clamped.)
• (float) ppmc.<port>.stepgen.<channel>.frequency -- Actual step pulse frequency in Hz (used mostly for troubleshooting.)
• (bit) ppmc.<port>.out.<channel>.invert -- Inverts a digital output, see canonical digital output.¹²

1.7.3 Functions

• (funct) ppmc.<port>.read -- Reads all inputs (digital inputs and encoder counters) on one port.
• (funct) ppmc.<port>.write -- Writes all outputs (digital outputs, stepgens, PWMs) on one port.

1.8 Pluto-P: generalities

The Pluto-P is an inexpensive ($60) FPGA board featuring the ACEX1K chip from Altera.

1.8.1 Requirements

1. A Pluto-P board
2. An EPP-compatible parallel port, configured for EPP mode in the system BIOS

1.8.2 Connectors

• The Pluto-P board is shipped with the left connector presoldered, with the key in the indicated position. The other connectors are unpopulated. There does not seem to be a standard 12-pin IDC connector, but some of the pins of a 16P connector can hang off the board next to QA3/QZ3.
• The bottom and right connectors are on the same .1" grid, but the left connector is not. If OUT2…OUT9 are not required, a single IDC connector can span the bottom connector and the bottom two rows of the right connector.

1.8.3 Physical Pins

• Read the ACEX1K datasheet for information about input and output voltage thresholds. The pins are all configured in "LVTTL/LVCMOS" mode and are generally compatible with 5V TTL logic.
• Before configuration and after properly exiting emc2, all Pluto-P pins are tristated with weak pull-ups (20kΩ min, 50kΩ max). If the watchdog timer is enabled (the default), these pins are also tristated after an interruption of communication between emc2 and the board. The watchdog timer takes approximately 6.5ms to activate. However, software bugs in the pluto_servo firmware or emc2 can leave the Pluto-P pins in an undefined state.
• In pwm+dir mode, by default dir is HIGH for negative values and LOW for positive values. To select HIGH for positive values and LOW for negative values, set the corresponding dout-NN-invert parameter TRUE to invert the signal.
• The index input is triggered on the rising edge. Initial testing has shown that the QZx inputs are particularly noise sensitive, due to being polled every 25ns. Digital filtering has been added to filter pulses shorter than 175ns (seven polling times). Additional external filtering on all input pins, such as a Schmitt buffer or inverter, RC filter, or differential receiver (if applicable) is recommended.
• The IN1…IN7 pins have 22-ohm series resistors to their associated FPGA pins. No other pins have any sort of protection for out-of-spec voltages or currents. It is up to the integrator to add appropriate isolation and protection. Traditional parallel port optoisolator boards do not work with pluto_servo due to the bidirectional nature of the EPP protocol.

1.8.4 LED

• When the device is unprogrammed, the LED glows faintly. When the device is programmed, the LED glows according to the duty cycle of PWM0 (LED = UP0 xor DOWN0) or STEPGEN0 (LED = STEP0 xor DIR0).

1.8.5 Power

• A small amount of current may be drawn from VCC. The available current depends on the unregulated DC input to the board. Alternately, regulated +3.3VDC may be supplied to the FPGA through these VCC pins. The required current is not yet known, but is probably around 50mA plus I/O current.
• The regulator on the Pluto-P board is a low-dropout type. Supplying 5V at the power jack will allow the regulator to work properly.

1.8.6 PC interface

• At present, only a single pluto_servo or pluto_step board is supported. At present there is no provision for multiple boards on one parallel port (because all boards reside at the same EPP address) but supporting one board per parallel port should be possible.

1.8.7 Rebuilding the FPGA firmware

The src/hal/drivers/pluto_servo_firmware/ and src/hal/drivers/pluto_step_firmware/ subdirectories contain the Verilog source code plus additional files used by Quartus for the FPGA firmwares. Altera's Quartus II software is required to rebuild the FPGA firmware. To rebuild the firmware from the .hdl and other source files, open the .qpf file and press CTRL-L. Then, recompile emc2.

Like the HAL hardware driver, the FPGA firmware is licensed under the terms of the GNU General Public License.

The gratis version of Quartus II runs only on Microsoft Windows, although there is apparently a paid version that runs on Linux.

1.8.8 For more information

The Pluto-P board may be ordered from http://www.knjn.com/ShopBoards_Parallel.html (US based, international shipping is available). Some additional information about it is available from http://www.fpga4fun.com/board_pluto-P.html and from the developer's blog.

1.9 pluto-servo: Hardware PWM and quadrature counting

The pluto_servo system is suitable for control of a 4-axis CNC mill with servo motors, a 3-axis mill with PWM spindle control, a lathe with spindle encoder, etc. The large number of inputs allows a full set of limit switches.

This driver features:

• 4 quadrature channels with 40MHz sample rate. The counters operate in "4x" mode. The maximum useful quadrature rate is 8191 counts per emc2 servo cycle, or about 8MHz for EMC2's default 1ms servo rate.
• 4 PWM channels, "up/down" or "pwm+dir" style. 4095 duty cycles from -100% to +100%, including 0%. The PWM period is approximately 19.5kHz (40MHz / 2047). A PDM-like mode is also available.
• 18 digital outputs: 10 dedicated, 8 shared with PWM functions. (Example: A lathe with unidirectional PWM spindle control may use 13 total digital outputs)
• 20 digital inputs: 8 dedicated, 12 shared with Quadrature functions. (Example: A lathe with index pulse only on the spindle may use 13 total digital inputs)
• EPP communication with the PC. The EPP communication typically takes around 100uS on machines tested so far, enabling servo rates above 1kHz.

1.9.1 Pinout

UPx

The "up" (up/down mode) or “pwm” (pwm+direction mode) signal from PWM generator X. May be used as a digital output if the corresponding PWM channel is unused, or the output on the channel is always negative. The corresponding digital output invert may be set to TRUE to make UPx active low rather than active high.

DNx

The "down" (up/down mode) or “direction” (pwm+direction mode) signal from PWM generator X. May be used as a digital output if the corresponding PWM channel is unused, or the output on the channel is never negative. The corresponding digital ouput invert may be set to TRUE to make DNx active low rather than active high.

QAx, QBx

The A and B signals for Quadrature counter X. May be used as a digital input if the corresponding quadrature channel is unused.

QZx

The Z (index) signal for quadrature counter X. May be used as a digital input if the index feature of the corresponding quadrature channel is unused.

INx

Dedicated digital input #x

OUTx

Dedicated digital output #x

GND

Ground

VCC

+3.3V regulated DC

Figure: Pluto-Servo Pinout

1.9.2 Input latching and output updating

• PWM duty cycles for each channel are updated at different times.
• Digital outputs OUT0 through OUT9 are all updated at the same time. Digital outputs OUT10 through OUT17 are updated at the same time as the pwm function they are shared with.
• Digital inputs IN0 through IN19 are all latched at the same time.
• Quadrature positions for each channel are latched at different times.

1.9.3 HAL Functions, Pins and Parameters

A list of all 'loadrt' arguments, HAL function names, pin names and parameter names is in the manual page, pluto_servo.9.

1.9.4 Compatible driver hardware

A schematic for a 2A, 2-axis PWM servo amplifier board is available (http://emergent.unpy.net/projects/01148303608). The L298 H-Bridge (L298 H-bridge) is inexpensive and can easily be used for motors up to 4A (one motor per L298) or up to 2A (two motors per L298) with the supply voltage up to 46V. However, the L298 does not have built-in current limiting, a problem for motors with high stall currents. For higher currents and voltages, some users have reported success with International Rectifier's integrated high-side/low-side drivers. (http://www.cnczone.com/forums/showthread.php?t=25929)

1.10 Pluto-step: 300kHz Hardware Step Generator

Pluto-step is suitable for control of a 3- or 4-axis CNC mill with stepper motors. The large number of inputs allows for a full set of limit switches.

The board features:

• 4 “step+direction” channels with 312.5kHz maximum step rate, programmable step length, space, and direction change times
• 14 dedicated digital outputs
• 16 dedicated digital inputs
• EPP communuication with the PC

1.10.1 Pinout

STEPx

The “step” (clock) output of stepgen channel x

DIRx

The “direction” output of stepgen channel x

INx

Dedicated digital input #x

OUTx

Dedicated digital output #x

GND

Ground

VCC

+3.3V regulated DC

While the “extended main connector” has a superset of signals usually found on a Step & Direction DB25 connector--4 step generators, 9 inputs, and 6 general-purpose outputs--the layout on this header is different than the layout of a standard 26-pin ribbon cable to DB25 connector.

Figure: Pluto-Step Pinout

1.10.2 Input latching and output updating

• Step frequencies for each channel are updated at different times.
• Digital outputs are all updated at the same time.
• Digital inputs are all latched at the same time.
• Feedback positions for each channel are latched at different times.

1.10.3 Step Waveform Timings

The firmware and driver enforce step length, space, and direction change times. Timings are rounded up to the next multiple of 1.6μs, with a maximum of 49.6μs. The timings are the same as for the software stepgen component, except that “dirhold” and “dirsetup” have been merged into a single parameter “dirtime” which should be the maximum of the two, and that the same step timings are always applied to all channels.

Figure: Pluto-Step Timings

1.10.4 HAL Functions, Pins and Parameters

A list of all 'loadrt' arguments, HAL function names, pin names and parameter names is in the manual page, pluto_step.9.

Index

• ACEX1K
• parallel port
• Pluto-P
• pluto-servo
• pluto-servo alternate pin functions
• pluto-servo pinout
• pluto-step
• pluto-step pinout
• pluto-step timings

Footnotes

1   HAL cannot automatically determine if the “x” mode bidirectional pins are actually open collectors (OC). If they are not, they cannot be used as inputs, and attempting to drive them LOW from an external source can damage the hardware. To determine whether your port has “open collector” pins, load hal_parport in “x” mode, output a HIGH value on the pin. HAL should read the pin as TRUE. Next, insert a 470Ω resistor from one of the control pins to GND. If the resulting voltage on the control pin is close to 0V, and HAL now reads the pin as FALSE, then you have an OC port. If the resulting voltage is far from 0V, or HAL does not read the pin as FALSE, then your port cannot be used in “x” mode. The external hardware that drives the control pins should also use open collector gates (e.g., 74LS05). Generally, the -out HAL pins should be set to TRUE when the physical pin is being used as an input. On some machines, BIOS settings may affect whether “x” mode can be used. “SPP” mode is most most likely to work. back

2   In the emc packages for Ubuntu, the file /etc/modprobe.d/emc2 generally prevents parport_pc from being automatically loaded. back

3   In fact it may be a pair of 8255 chips, but I'm not sure. If/when someone starts a driver for an 8255 they should look at the ax5214 code, much of the work is already done. back

4   a motion control card usually is a board containing devices to control one or more axes (the control devices are usually DAC's to set an analog voltage, encoder counting chips for feedback, etc.) back

5   hint: after starting up the driver, 'dmesg' can be consulted for messages relevant to the driver (e.g. autodetected version number and base address) back

6   if IIOO is defined, there are 16 input pins (in-00 .. in-15) and 16 output pins (out-00 .. out-15), and they correspond to PORTs ABCD (in-00 is PORTA.0, out-15 is PORTD.7) back

7   Ideally the encoders, “DACs”, and digital I/O would comply with the canonical interfaces defined earlier, but they don't. Fixing that is on the things-to-do list. back

8   With normal 10 bit PWM, 50% duty cycle would be 512 cycles on and 512 cycles off = ca 30 kHz with 33 MHz reference counter. With fully interleaved PWM this would be 1 cycle on, 1 cycle off for 1024 cycles (16.66 MHz if the PWM reference counter runs at 33 MHz) = much easier to filter. The 5I20 configuration interlace is somewhat between non and fully interlaced (to make it easy to filter but not have as many transistions as fully interleaved). back

9   emc2/src/hal/drivers/m5i20/REGMAP4E back

10   Ideally the encoders, DACs, ADCs, and digital I/O would comply with the canonical interfaces defined earlier, but they don't. Fixing that is on the things-to-do list. back

11   Index handling does _not_ comply with the canonical encoder interface, and should be changed. back

12   In a future version this will be changed from .invert to -invert to better match the HAL canonical bit interface back